1. Field of Invention
This invention relates generally to the field of computer aided design and analysis of structural systems, such as integrated circuits, and more particularly to systems and methods for optimizing performance criteria, such as fabrication yield for such structural systems.
2. Background of Invention
Integrated circuits are one type of structural system commonly designed using computer aided design systems. As with many structural systems, integrated circuits are designed while attempting to satisfy and preferably optimize numerous performance criteria. One such performance criteria is fabrication yield.
Yield is determined in part by the number of electrical failures on a wafer. One of the main sources of electrical failure in VLSI integrated circuits is the presence of spot defects. Spot defects are typically caused by either extra material or missing material at the place where the spot defect occurs. Modeling of the spot defect size distribution is typically used in the calculation of minimum design rules in order to specify the location of circuit elements to reduce the number of spot defects. The choice of the minimum design rules results from a trade off between area and yield considerations. Yield can be increased by using bigger feature sizes and wider spacings than the minimum required by the design rules to reduce spot defects. Therefore, to improve yield it is beneficial to use non-minimum spacings whenever this does not introduce significant area penalty. Due to the very high costs associated with the manufacturing of sub-micron integrated circuits, even a modest yield improvement can be extremely significant. For instance in a modern deep-submicron foundry a 1% yield improvement can be worth over 10M$ per year
At the layout design level, conventional methods for improving yield due to spot defect failures fall into two broad complementary categories. In the first category the layout topology is changed to improve yield. This generally involves changing the routing of the components in the layout. Channel routing techniques have been used to minimize the critical areas between wire segments, so that bridging defects are minimized. Also, in a weight-driven area routing approach, the types of faults due to spot defects are considered, using the distributions of spot defects to build a cost function. Although these routing-based approaches have proved somewhat effective in increasing yield, routing is a constructive procedure, whose results are sensitive to net schedule.
In the second category of methods for yield improvement the layout topology is fixed. Components and interconnections are spaced to minimize the probability of faults due to spot defects. One such spacing-based approach uses a heuristic algorithm that increases the spacing of layout objects through a series of spacing iterations. By changing the positions of only objects off the critical path, layout area is maintained at its minimum size.
The above mentioned methods not only do not produce a guaranteed optimized yield but cannot be extended to other performance objectives. Yield is merely one of the performance criteria that must be optimized during integrated circuit design and fabrication. Most industrial applications require the simultaneous optimization of multiple performance objectives in addition to yield, such as power consumption, cross-talk, and wire length.
This problem of simultaneous optimization of multiple criteria is especially difficult to solve. Channel routing typically uses heuristically determined methods that do not support the simultaneous solution of yield and other performance criteria. On the other hand, conventional spacing methods typically rely on cost functions that are linear. However, the cost functions for yield, power, and the like, are non-linear, but rather, convex.
Accordingly, it is desirable to provide a system and method that produces an optimized yield for an integrated circuit. It is further desirable to provide a system and method that simultaneously optimizes a variety of distinct performance criteria having non-linear convex cost functions.